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1 typical a pplica t ion fea t ures a pplica t ions descrip t ion 1a buck-boost dc/dc and dual 600ma buck dc/dc converters the lt c ? 3521 combines a 1 a buck- boost dc/ dc converter and dual 600 ma synchronous buck dc / dc converters. the 1.1mhz switching frequency minimizes the solution foot - print while maintaining high efficiency. all three converters feature soft-start and internal compensation to minimize the solution footprint and simplify the design process. the buck converters are current mode controlled and utilize an internal synchronous rectifier to improve ef - ficiency. the buck converters support 100% duty cycle operation to extend battery life. if the pwm pin is held low, the buck converters automatically transition from burst mode operation to pwm mode at high loads. with the pwm pin held high, the buck converters remain in low noise, 1.1mhz pwm mode. the buck- boost converter features continuous conduction operation to maximize efficiency and minimize noise. at light loads, the buck-boost converter can be operated in burst mode operation to improve efficiency and reduce no-load standby current. the ltc3521 provides a <2 a shutdown mode, over- temperature shutdown and current limit protection on all converters. the ltc3521 is available in a 24-pin 0.75mm 4mm 4 mm qfn package, and a 20- pin ther- mally enhanced tssop package. n three high efficiency dc/dc converters: buck-boost (v out : 1.8v to 5.25v, i out : 1a) dual buck (v out : 0.6v to v in , i out : 600ma) n 1.8v to 5.5v input voltage range n pin-selectable burst mode ? operation n 30a total quiescent current in burst mode operation n independent power good indicator outputs n integrated soft-start n thermal and overcurrent protection n <2a current in shutdown n small 4mm 4mm qfn and thermally enhanced tssop packages n bar code readers n medical instruments n handy terminals n pdas, handheld pcs n gps receivers + pv in1 pv in2 sw2 sw3 fb2 fb3 v out1 ltc3521 shdn2 shdn1 1.0m 137k 68.1k 22f 10f v in 4.7f li-ion 4.7h 4.7h v out1 3.3v 800ma (1a, v in > 3.0v) v out2 1.8v 600ma 100k 100k 10f 4.7h v out3 1.2v 600ma v in 2.4v to 4.2v 221k 3521 ta01a shdn3 pwm sw1a sw1b fb1 pgood2 pgood1 pgood3 pgnd1a pgnd2 gnd pgnd1b on off pwm burst v in (v) 2.4 efficiency (%) 92 94 96 98 5.4 3521 ta01b 88 90 86 84 82 80 76 78 74 72 70 3.4 4.4 100 v out1 = 3.3v i out = 500ma v out2 = 1.8v i out = 200ma v out3 = 1.2v i out = 200ma efficiency vs v in l, lt , lt c , lt m , linear technology, burst mode and the linear logo are registered trademarks and powerpath is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u. s. patents, including 6404251, 6166527. ltc3521 3521fb for more information www.linear.com/ltc3521
2 p in c on f igura t ion a bsolu t e maxi m u m r a t ings pv in 1 , pv in 2 , v in voltage ............................. C0. 3 v to 6v sw1a, sw1b, sw 2, sw3 voltage dc ............................................................ C 0.3 v to 6v pul sed < 100 ns ............................................ C1 v to 7v (note 1) lead free finish tape and reel part marking* package description temperature range ltc3521efe#pbf ltc3521efe#trpbf ltc3521fe 20-lead plastic tssop C40c to 125c ltc3521ife#pbf ltc3521ife#trpbf ltc3521fe 20-lead plastic tssop C40c to 125c ltc3521euf#pbf ltc3521euf#trpbf 3521 24-lead (4mm 4mm) plastic qfn C40c to 125c ltc3521iuf#pbf ltc3521iuf#trpbf 3521 24-lead (4mm 4mm) plastic qfn C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ o r d er i n f or m a t ion voltage , all other pins ................................. C 0.3 v to 6v operating junction temperature range ( n otes 2, 5) ............................................ C 40 c to 125 c storage temperature range .................. C 65 c to 150 c fe package 20-lead plastic tssop 1 2 3 4 5 6 7 8 9 10 top view 20 19 18 17 16 15 14 13 12 11 fb3 fb2 shdn2 pgood3 pgood2 pgood1 v in gnd pwm fb1 pv in2 sw2 pgnd2 sw3 v out1 sw1a sw1b pv in1 shdn1 shdn3 21 pgnd1a t jmax = 150c, ja = 40c/w (note 4) underside metal internally connected to v C (pcb connection optional) exposed pad (pin 21) is pgnd1a and must be soldered to pcb ground 24 23 22 21 20 19 7 8 9 top view 25 pgnd1a uf package 24-lead (4mm 4mm) plastic qfn 10 11 12 6 5 4 3 2 1 13 14 15 16 17 18 shdn2 pgood3 pgood2 pgood1 v in gnd pgnd2 sw3 v out1 sw1a sw1b nc fb2 fb3 pv in2 pgnd1a sw2 nc pwm fb1 shdn3 shdn1 pv in1 pgnd1b t jmax = 125c, ja = 37c/w exposed pad ( pin 25) is pgnd1a and must be soldered to pcb ground ltc3521 3521fb for more information www.linear.com/ltc3521
3 note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3521 is tested under pulsed load conditions such that t j t a . the ltc3521e is guaranteed to meet performance specifica- parameter conditions min typ max units input voltage l 1.8 5.5 v quiescent currentshutdown v shdn1 = v shdn2 = v shdn3 = 0v (note 6) l 0.01 2 a burst mode quiescent current v fb1 = 0.66v, v fb2 = 0.66v, v fb3 = 0.66v, v pwm = 0v 30 a oscillator frequency l 0.85 1.1 1.35 mhz shdn1, shdn2, shdn3, pwm input high voltage l 1.4 v shdn1, shdn2, shdn3, pwm input low voltage l 0.4 v power good outputs low voltage i pgood1 = i pgood2 = i pgood3 = 1ma 0.1 0.2 v power good outputs leakage current v pgood1 = v pgood2 = v pgood3 = 5.5v 0.1 10 a buck converters pmos switch resistance 0.205 nmos switch resistance 0.170 nmos switch leakage current v sw2 = v sw3 = 5.5v, v in = 5.5v 0.1 5 a pmos switch leakage current v sw2 = v sw3 = 0v, v in = 5.5v 0.1 10 a feedback voltage (note 4) l 0.585 0.6 0.612 v feedback input current v fb2 = v fb3 = 0.6v 1 50 na pmos current limit (note 3) l 750 1050 ma maximum duty cycle v fb2 = v fb3 = 0.55v l 100 % minimum duty cycle v fb2 = v fb3 = 0.66v l 0 % pgood threshold v fb2,3 falling C12 C9 C6 % power good hysteresis v fb2,3 returning good 2 % buck-boost converter output voltage l 1.8 5.25 v pmos switch resistance 0.110 nmos switch resistance 0.085 nmos switch leakage current v sw1a = v sw1b = 5.5v, v in = 5.5v 0.1 5 a pmos switch leakage current v sw1a = v sw1b = 0v, v in = 5.5v 0.1 10 a feedback voltage (note 4) l 0.585 0.6 0.612 v feedback input current v fb1 = 0.6v 1 50 na average current limit (note 3) l 1.65 2.1 a reverse current limit (note 3) 375 ma maximum duty cycle v fb1 = 0.55v l 85 94 % minimum duty cycle v fb1 = 0.66v l 0 % pgood threshold v fb1 falling C12 C9 C6 % power good hysteresis v fb1 returning good 3 % e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in , pv in1 , pv in2 = 3.6v, v out1 = 3.3v, unless otherwise noted. tions from 0c to 85c. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3521i is guaranteed over the full C40c to 125c operating junction temperature range. the maximum ambient temperature is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. ltc3521 3521fb for more information www.linear.com/ltc3521
4 typical p er f or m ance c harac t eris t ics buck-boost efficiency vs load current, li-ion to 3.3v buck efficiency vs load current, li-ion to 2.5v buck efficiency vs load current, li-ion to 1.8v buck burst mode current threshold vs v in 0.1 1 10 100 1000 load current (ma) efficiency (%) power loss (mw) 3521 g01 0 20 40 60 80 100 120 140 0 20 30 40 50 60 70 80 90 100 10 burst mode operation burst mode power loss v in = 2.7v v in = 4.2v pwm mode 0.1 1 10 100 1000 load current (ma) 0 efficiency (%) power loss (mw) 20 30 40 50 60 70 3521 g02 80 90 100 0 20 40 60 80 100 120 140 10 burst mode operation burst mode power loss v in = 3.6v v in = 4.2v pwm mode 0.1 1 10 100 1000 load current (ma) 0 efficiency (%) power loss (mw) 20 30 40 50 60 70 3521 g03 80 90 100 0 20 40 60 80 100 120 140 10 burst mode operation burst mode power loss pwm mode v in = 2.7v v in = 4.2v t a = 25c, unless otherwise noted. v in (v) 1.5 load current (ma) 40 50 5 30 20 2.5 3.5 2 3 4 4.5 5.5 10 0 60 3521 g04 v out = 2.5v v out = 1.8v v out = 1.2v e lec t rical c harac t eris t ics note 3: current measurements are performed when the ltc3521 is not switching. the current limit values in operation will be somewhat higher due to the propagation delay of the comparators. note 4: the ltc3521 is tested in a proprietary test mode that connects each fb pin to the output of the respective error amplifier. note 5: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 6: shutdown current is measured on the v in pin and does not include pmos switch leakage. ltc3521 3521fb for more information www.linear.com/ltc3521
5 switching frequency vs temperature buck-boost feedback voltage vs temperature typical p er f or m ance c harac t eris t ics buck feedback voltage vs temperature buck-boost maximum load current vs v in , burst mode operation buck-boost switches r ds(on) vs temperature buck switches r ds(on) vs temperature switching frequency vs v in t a = 25c, unless otherwise noted. burst mode quiescent current vs v in temperature (c) ?40 r ds(on) (m) 120 140 100 100 80 0 40 ?20 20 60 120 80 20 0 60 160 40 3521 g05 pmos (switches a and d) nmos (switches b and c) v in = 3.6v v out1 = 3.3v temperature (c) ?40 r ds(on) (m) 300 100 250 200 0 40 ?20 20 60 120 80 50 0 150 350 100 3521 g06 pmos nmos v in = 3.6v temperature (c) ?50 ?1.0 change from 25c (%) ?0.8 ?0.4 ?0.2 0 1.0 0.4 ?10 30 50 3521 g07 ?0.6 0.6 0.8 0.2 ?30 10 70 90 110 v in (v) 1.8 change from v in = 3.6v (%) 1.0 1.5 5.3 0.5 0 2.8 3.8 2.3 3.3 4.3 4.8 ?1.5 ?2.0 ?0.5 2.0 ?1.0 3521 g08 temperature (c) ?40 change in feedback voltage from 25c (%) 0.1 100 0 ?0.1 0 40 ?20 20 60 120 80 ?0.4 ?0.5 ?0.2 0.2 ?0.3 3521 g09 temperature (c) change in feedback voltage from 25c (%) ?0.1 0 0.1 ?0.2 ?0.3 ?0.4 ?0.5 0.2 3521 g10 ?50 ?25 250 50 75 100 125 v in (v) 1.8 quiescent current (a) 5.3 31 2.8 3.8 2.3 3.3 4.3 4.8 25 29 33 27 3521 g11 all three converters enabled v in (v) 1.8 maximum load current (ma) 60 70 80 5.3 50 40 2.8 3.8 2.3 3.3 4.3 4.8 10 0 30 90 20 3521 g12 v out = 3v v out = 5v buck-boost maximum load current vs v in , pwm mode 100 500 900 1300 300 700 1100 1500 v in (v) load current (ma) 3521 g13 v out = 3.3v l = 4.7h v out = 5v 1.8 5.3 2.8 3.8 2.3 3.3 4.3 4.8 ltc3521 3521fb for more information www.linear.com/ltc3521
6 typical p er f or m ance c harac t eris t ics buck-boost current limit vs temperature buck current limit vs temperature t a = 25c, unless otherwise noted. buck-boost peak current limit vs temperature temperature (c) current limit (ma) 2100 2050 2000 1950 2150 3521 g19 ?50 ?25 250 50 75 100 125 temperature (c) current limit (ma) 3300 3250 3200 3350 3521 g20 ?50 ?25 250 50 75 100 125 temperature (c) current limit (ma) 1100 1050 1000 950 900 1150 3521 g21 ?50 ?25 250 50 75 100 125 50s/div v out 20mv/div inductor current 200ma/div 3521 g16 v in = 3.6v v out = 3.3v l = 4.7h c out = 22f buck-boost burst mode operation to pwm transition buck load step, pwm mode, 10ma to 400ma buck load step, burst mode, 10ma to 400ma 100s/div v out 100mv/div inductor current 200ma/div 3521 g17 v in = 3.6v v out = 1.8v l = 4.7h c out = 10f 100s/div v out 100mv/div inductor current 200ma/div 3521 g18 v in = 3.6v v out = 1.8v l = 4.7h c out = 10f no load quiescent current vs v in 100s/div v out 100mv/div inductor current 500ma/div 3521 g15 v in = 3.6v, v out = 3.3v l = 4.7h c out = 22f buck-boost load step, 0ma to 750ma v in (v) 1.8 quiescent current (a) 5.3 2.8 3.8 2.3 3.3 4.3 4.8 45 40 55 60 50 3521 g14 ltc3521 3521fb for more information www.linear.com/ltc3521
7 p in func t ions fb3 (pin 1/pin 23): feedback voltage for the buck con- verter derived from a resistor divider connected to the buck v out3 output voltage. the buck output voltage is given by the following equation, where r1 is a resistor between fb3 and ground, and r2 is a resistor between fb3 and the buck output voltage: v out3 = 0.6v 1 + r2 r1 ? ? ? ? ? ? fb2 (pin 2/pin 24): feedback voltage for the buck con- verter derived from a resistor divider connected to the buck v out2 output voltage. the buck output voltage is given by the following equation, where r1 is a resistor between fb2 and ground, and r2 is a resistor between fb2 and the buck output voltage: v out2 = 0.6v 1 + r2 r1 ? ? ? ? ? ? shdn2 (pin 3/pin 1): forcing this pin above 1.4 v enables the buck converter output at sw2. forcing this pin below 0.4v disables the buck converter. this pin cannot be left floating. pgood3 (pin 4/pin 2): this pin is an open-drain output which pulls low under any of the following conditions: v out3 buck output voltage is out of regulation, the part is in overtemperature shutdown, the part is in undervoltage lockout, or the shdn3 pin is pulled low. pgood2 (pin 5/pin 3): this pin is an open-drain output which pulls low under any of the following conditions: v out2 buck output voltage is out of regulation, the part is in overtemperature shutdown, the part is in undervoltage lockout, or the shdn2 pin is pulled low. pgood1 (pin 6/pin 4): this pin is an open-drain output which pulls low under any of the following conditions: v out1 buck-boost output voltage is out of regulation, the part is in overtemperature shutdown, the part is in un- dervoltage lockout, the buck-boost converter is in current limit, or the shdn1 pin is pulled low. see the operation section of this data sheet for details on the functionality of this pin in pwm mode. v in (pin 7/pin 5): low current power supply connection used to power the internal circuitry of the ltc3521. this pin should be bypassed by a 4.7 f, or larger, ceramic capacitor. the bypass capacitor should be placed as close to the pin as possible and should have a short return path to ground. pins v in , pv in1 , and pv in2 must be connected together in the application circuit. gnd ( pin 8/pin 6): small signal ground. this pin is used as a ground reference for the internal circuitry of the ltc3521. pwm (pin 9/pin 7): logic input used to choose between burst mode operation and pwm mode for all three con- verters. this pin cannot be left floating. pwm = low: burst mode operation is enabled on all three converters. the buck converters will operate in burst mode operation at light current but will automati- cally transition to pwm operation at high currents. the buck converters can supply maximum output current (600ma) in this mode . the buck-boost converter will operate in variable frequency mode and can only supply a reduced load current (typically 50ma). pwm = high: all three converters are forced into pwm mode operation. the buck converters will remain at constant-frequency operation until their minimum on- time is reached. the buck-boost converter will remain in pwm mode at all load currents. fb1 (pin 10/pin 8): feedback voltage for the buck-boost converter derived from a resistor divider on the buck- boost output voltage. the buck-boost output voltage is given by the following equation, where r1 is a resistor between fb1 and ground, and r2 is a resistor between fb1 and the buck output voltage: v out1 = 0.6v 1 + r2 r1 ? ? ? ? ? ? shdn3 (pin 11/pin 9): forcing this pin above 1.4 v en- ables the buck converter output at sw3. forcing this pin below 0.4 v disables the buck converter. this pin cannot be left floating. shdn1 (pin 12/pin 10): forcing this pin above 1.4v enables the buck-boost converter. forcing this pin below 0.4v disables the buck-boost converter. this pin cannot be left floating. (fe/uf packages) ltc3521 3521fb for more information www.linear.com/ltc3521
8 pv in1 (pin 13/pin 11): high current power supply connec- tion used to supply switch a of the buck-boost converter . this pin should be bypassed by a 4.7 f, or larger, ceramic cap. the bypass capacitor should be placed as close to the pin as possible and should have a short return path to ground. pins v in , pv in1 , and pv in2 must be connected together in the application circuit. nc (pin 13, uf package only): no internal connection. sw 1b ( pin 14/pin 14): buck- boost switch node. this pin must be connected to one side of the buck- boost inductor. sw 1a ( pin 15/pin 15): buck- boost switch node. this pin must be connected to one side of the buck- boost inductor. v out1 (pin 16/pin 16): buck-boost output voltage node. this pin should be connected to a low esr ceramic ca- pacitor. the capacitor should be placed as close to the ic as possible and should have a short return to ground. sw3 (pin 17/pin 17): buck converter switch node. this pin must be connected to the opposite side of the inductor connected to v out3 . pgnd2 (pin 18/pin 18): high current ground connection for both buck converters. the pcb trace conn ecting this pin to ground should be made as short and wide as possible. sw2 (pin 19/pin 20): buck converter switch node. this pin must be connected to the opposite side of the inductor connected to v out2 . nc (pin 19, uf package only): no internal connection. pv in 2 ( pin 20/ pin 22): high current power supply connec - tion used to supply the buck converter power switches. this pin should be bypassed by a 10 f or larger ceramic cap. the bypass capacitor should be placed as close to the pin as possible and should have a short return path to ground. pins v in , pv in1 , and pv in2 must be connected together in the application circuit. pgnd1a ( exposed pad pin 21/pin 21, exposed pad pin 25): high current ground connection for the buck- boost switch b. the pcb trace connecting this pin to ground should be made as short and wide as possible. pgnd 1b ( pin 12, uf package only): high current ground connection for the buck-boost switch c. the pcb trace connecting this pin to ground should be made as short and wide as possible. p in func t ions (fe/uf packages) ltc3521 3521fb for more information www.linear.com/ltc3521
9 b lock diagra m + ? + ? pgood1 pv out 4 16 fb1 shdn1 filter reverse i limit forward i limit 21 0.546v 2.1a 0.375a + ? + ? 0a i zero buck-boost pwm logic gate drives gate drives buck pwm logic bandgap reference and ot shutdown oscillator uvlo 0.6v soft-start ramp + + ? soft-start ramp 10 shdn2 1 shdn3 9 8 d v out1 14 sw1b 15 sw1a 11 pv in1 22 pv in2 cb a pgnd1b pgnd1a pgnd2 zero crossing 5 v in 7 pwm internal v cc 20 sw2 fb2 + ? 0a + ? + ? 1.05a i limit 0.546v 3521 bd 0.60v g m pgnd1a 6 gnd 12 pgnd1b 18 pgnd2 slope compensation + + ? 24 pgood2 + + ? 1.2v 0.6v 0.546v 0.25v 3 pv in2 gate drives buck pwm logic soft-start ramp pgnd2 zero crossing 17 sw3 fb3 + ? 0a + ? + ? 1.05a i limit 0.546v 0.60v g m slope compensation + + ? 23 pgood3 + + ? 2 pv in2 (uf package) ltc3521 3521fb for more information www.linear.com/ltc3521
10 o pera t ion the ltc3521 combines dual synchronous buck dc/dc converters and a 4- switch buck-boost dc/dc converter in a 4 mm 4 mm qfn package and a 20- pin thermally enhanced tssop package. the buck-boost converter utilizes a proprietary switching algorithm which allows its output voltage to be regulated above, below or equal to the input voltage. the buck converters provide a high ef - ficiency lower voltage output and support 100% duty cycle operation to extend battery life. in burst mode operation, the total quiescent current for the ltc3521 is reduced to 30a. all three converters are synchronized to the same internal 1.1mhz oscillator. b uck c onver ter o pera tion pwm mode operation when the pwm pin is held high, the ltc3521 buck con - verters use a constant-frequency, current mode control ar chitecture. both the main ( p-channel mosfet) and synchronous rectifier ( n- channel mosfet) switches are internal. at the start of each oscillator cycle, the p-channel switch is turned on and remains on until the current waveform with superimposed slope compensation ramp exceeds the error amplifier output. at this point, the synchronous rectifier is turned on and remains on until the inductor current falls to zero or a new switching cycle is initiated. as a result, the buck converters operate with discontinuous inductor current at light loads, which improves efficiency. at extremely light loads, the minimum on-time of the main switch will be reached and the buck converters will begin turning off for multiple cycles in order to maintain regulation. burst mode operation when the pwm pin is forced low, the buck converters will automatically transition between burst mode operation at sufficiently light loads ( below approximately 15ma) and pwm mode at heavier loads. burst mode entry is determined by the peak inductor current. therefore , the load current at which burst mode operation will be entered depends on the input voltage, the output voltage and the inductor value. typical curves for burst mode entry threshold are provided in the typical performance characteristics section of this data sheet. in dropout and near dropout conditions, burst mode operation is disabled. dropout operation as the input voltage decreases to a value approaching the output regulation voltage, the duty cycle increases toward the maximum on-time. further reduction of the supply voltage will force the main switch to remain on for more than one cycle until 100% duty cycle operation is reached where the main switch remains on continuously. in this dropout state, the output will be determined by the input voltage less the resistive voltage drop across the main switch and series resistance of the inductor. slope compensation current mode control requires the use of slope compensa - tion to prevent subharmonic oscillations in the inductor current at high duty cycle operation. this is accomplished internally on the ltc3521 through the addition of a com - pensating ramp to th e current sense signal. in some current mode ics, current limiting is performed by clamping the error amplifier voltage to a fixed maximum. this leads to a reduced output current capability at low step-down ratios. in contrast, the ltc3521 performs current limiting prior to addition of the slope compensation ramp and therefore achieves a peak inductor current limit that is independent of duty cycle. short-circuit protection when the output is shorted to ground, the error amplifier will saturate high and the p-channel mosfet switch will turn on at the start of each cycle and remain on until the current limit trips. during this minimum on-time, the in - ductor current will increase rapidly and will decrease very slowly during the remainder of the period due to the ver y small reverse voltage produced by a hard output short. to eliminate the possibility of inductor current runaway in this situation, the buck converter switching frequency is reduced to 250 khz when the voltage on the buck fb pin falls below 0.25 v. the buck soft-start circuit is reset when the buck fb pin falls below 0.25 v to provide a smooth restart once the short-circuit condition at the output voltage is no longer present. additionally, the pmos current limit is decreased from 1050 ma to 700 ma when the voltage on the buck fb pin falls below 0.25v. ltc3521 3521fb for more information www.linear.com/ltc3521
11 soft-start the buck converters have an internal voltage mode soft-start circuit with a nominal duration of 800 s. the converters remain in regulation during soft-start and will therefore respond to output load transients which occur during this time. in addition, the output voltage rise time has minimal dependency on the size of the output capaci - tor or load current. error amplifier and compensation the ltc3521 buck converters utilize an internal transcon- ductance error amplifier. compensation of the feedback loop is performed internally to reduce the size of the application circuit and simplify the design process. the compensation network has been designed to allow use of a wide range of output capacitors while simultaneously ensuring rapid response to load transients. pgood comparators the pgood2 and pgood3 pins are open- drain outputs which indicate the status of the buck converters. if the buck output voltage falls 9% below the regulation voltage, the respective pgood open- drain output will pull low. the output voltage must rise 2% above the falling threshold before the pull- down will turn off. in addition, there is a 60 s typical deglitching delay in the flag in order to prevent false trips due to voltage transients on load steps. the respective pgood output will also pull low during overtemperature shutdown, undervoltage lockout or if the respective buck con - verter shdn pin is pulled low to indicate these fault conditions. b uck -b oost c onverter o peration pwm mode operation when the pwm pin is held high, the ltc3521 buck-boost converter operates in a constant-frequency pwm mode with voltage mode control. a proprietary switching algo - rithm allows the converter to switch between buck, buck- boost and boost modes without discontinuity in inductor current or loop characteristics. the switch topology for the buck-boost converter is shown in figure 1. when the input voltage is significantly greater than the output voltage, the buck-boost converter operates in buck mode. switch d turns on continuously and switch c remains off. switches a and b are pulse width modu - lated to produce the required duty cycle to support the output regulation voltage. as the input voltage decreases, switch a remains on for a larger portion of the switching cycle. when the duty cycle reaches approximately 85%, the switch pair ac begins turning on for a small fraction of the switching period. as the input voltage decreases further, the ac switch pair remains on for longer durations and the duration of the bd phase decreases proportion- ally. as the input voltage drops below the output voltage, the ac phase will eventually increase to the point that there is no longer any bd phase. at this point, switch a remains on continuously while switch pair cd is pulse width modulated to obtain the desired output voltage. at this point, the converter is operating solely in boost mode. this switching algorithm provides a seamless transition between operating modes and eliminates discontinuities in average inductor current, inductor current ripple and loop transfer function throughout all three operational o pera t ion l d pgnd1b pgnd1a ltc3521 a sw1a sw1b b c 3521 f01 v out1 pv in1 figure 1. buck-boost switch topology ltc3521 3521fb for more information www.linear.com/ltc3521
12 modes. these advantages result in increased efficiency and stability in comparison to the traditional 4-switch buck-boost converter. error amplifier and compensation the buck-boost converter utilizes a voltage mode error amplifier with an internal compensation network as shown in figure 2. this case, the increased bandwidth created by decreasing r2 is used to counteract the reduced converter bandwidth caused by the large output capacitor. current limit operation the buck-boost converter has two current limit circuits. the primary current limit is an average current limit circuit which injects an amount of current into the feedback node which is proportional to the extent that the switch a cur - rent exceeds the current limit value. due to the high gain of this loop, the injected current forces the error amplifier output to decrease until the average current through switch a decreases approximately to the current limit value. the average current limit utilizes the error amplifier in an active state and thereby provides a smooth recovery with little overshoot once the current limit fault condition is removed. since the current limit is based on the average current through switch a, the peak inductor current in current limit will have a dependency on the duty cycle ( i.e., on the input and output voltages in the overcurrent condition). the speed of the average current limit circuit is limited by the dynamics of the error amplifier. on a hard output short, it would be possible for the inductor current to increase substantially beyond current limit before the average cur - rent limit circuit would react. for this reason, there is a second current limit circuit which turns off switch a if the current ever exceeds approximately 165% of the average current limit value. this provides additional protection in the case of an instantaneous hard output short. reverse current limit the reverse current comparator on switch d monitors the inductor current entering pv out . when this current exceeds 375ma ( typical), switch d will be turned off for the remainder of the switching cycle. o pera t ion 0.6v gnd pv out ltc3521 v out fb1 r2 r1 3521 f02 + ? figure 2. buck-boost error amplifier and compensation notice that resistor r2 of the external resistor divider network plays an integral role in determining the frequency response of the compensation network. the ratio of r2 to r1 must be set to program the desired output voltage but this still allows the value of r2 to be adjusted to optimize the transient response of the converter. increasing the value of r2 generally leads to greater stability at the expense of reduced transient response speed. increasing the value of r 2 can yield substantial transient response improvement in cases where the phase margin has been reduced due to the use of a small value output capacitor or a large inductance (particularly with large boost step-up ratios). conversely, decreasing the value of r2 increases the loop bandwidth which can improve the speed of the converters transient response. this can be useful in improving the transient response if a large valued output capacitor is utilized. in ltc3521 3521fb for more information www.linear.com/ltc3521
13 burst mode operation with the pwm pin held low, the buck-boost converter operates utilizing a variable frequency switching algorithm designed to improve efficiency at light load and reduce the standby current at zero load. in burst mode operation, the inductor is charged with fixed peak amplitude current pulses. these current pulses are repeated as often as necessary to maintain the output regulation voltage. the maximum output current which can be supplied in burst mode operation is dependent upon the input and output voltage as given by the following formula: i out(max),burst = 0.1 ? v in v in + v out a ( ) in burst mode operation, the error amplifier is not used but is instead placed in a low current standby mode to reduce supply current and improve light load efficiency. soft-start the buck-boost converter has an internal voltage mode soft-start circuit with a nominal duration of 600 s. the converter remains in regulation during soft-start and will therefore respond to output load transients that occur during this time. in addition, the output voltage rise time has minimal dependency on the size of the output capaci- tor or load. during soft-start, the buck-boost converter is for ced into pwm operation regardless of the state of the pwm pin. pgood comparator the pgood1 pin is an open-drain output which indicates the status of the buck-boost converter. in burst mode operation ( pwm = low), the pgood1 open-drain output will pull low when the feedback voltage falls 9% below the regulation voltage. there is approximately 3% hysteresis in this threshold when the output voltage is returning good. in addition, there is a 60 s typical deglitching delay to prevent false trips due to short duration voltage transients in response to load steps. in pwm mode, operation of the pgood1 comparator is complicated by the fact that the feedback pin voltage is driven to the reference voltage independent of the output o pera t ion voltage through the action of the voltage mode error am- plifier. s ince the soft-start is voltage mode, the feedback voltage will track the output voltage correctly during soft-start, and the pgood1 output will correctly indicate the point at which the buck-boost attains regulation at the end of soft-start. therefore, the pgood1 output can be utilized for sequencing purposes. once in regulation, the feedback voltage will no longer track the output voltage, and the pgood1 pin will not directly respond to a loss of regulation in the output. however, the only means by which a loss of regulation can occur is if the current limit has been reached, thereby preventing the buck-boost converter from delivering the required output current. in such cases, the occurrence of current limit will cause the pgood1 flag to fall indicating a fault state. there can be cases, however, when the buck-boost converter is continuously in current limit, causing the pgood1 output to pull low, while the output voltage still remains slightly above the pgood1 comparator trip point. the pgood1 output also pulls low during overtemperature shutdown, undervoltage lockout or if the shdn1 pin is pulled low. c ommon f unctions thermal shutdown if the die temperature exceeds 150 c, all three converters will be disabled. all power devices will be turned off and all switch nodes will be high impedance. the soft-start circuits for all three converters are reset during thermal shutdown to provide a smooth recovery once the over - temperature condition is eliminated. all three converters will restart ( if enabled) when the die temperature drops to approximately 140c. undervoltage lockout if the supply voltage decreases below 1.7v ( typical) then all three converters will be disabled and all power devices will be turned off. the soft-start circuits for all three con - verters are reset during undervoltage lockout to provide a smooth restart once the input voltage rises above the undervoltage lockout threshold. ltc3521 3521fb for more information www.linear.com/ltc3521
14 a pplica t ions i n f or m a t ion the basic ltc3521 application circuit is shown as the typical application on the front page of this data sheet. the external component selection is determined by the desired output voltages, output currents and ripple volt - age requirements of each particular application. basic guidelines and considerations for the design process are provided in this section. buck inductor selection the choice of buck inductor value influences both the ef - ficiency and the magnitude of the output voltage ripple. larger inductance values will reduce inductor current ripple and lead to lower output voltage ripple. for a fixed dc resistance, a larger value inductor will yield higher efficiency by lowering the peak current closer to the av - erage. however , a larger inductor within the same family will generally have a greater series resistance, thereby offsetting this efficiency advantage. given a desired peak- to- peak current ripple, i l , the required inductance can be calculated via the following expression, where f represents the switching frequency in mhz: l = 1 f i l v out 1C v out v in ? ? ? ? ? ? h ( ) a reasonable choice for ripple current is i l = 240ma which represents 40% of the maximum 600 ma load current. the dc current rating of the inductor should be at least equal to the maximum load current, plus half the ripple current, in order to prevent core saturation and loss of efficiency during operation. to optimize efficiency, the inductor should have a low series resistance. in particularly space-restricted applications, it may be advantageous to use a much smaller value inductor at the expense of larger ripple current. in such cases, the converter will operate in discontinuous conduction for a wider range of output loads and efficiency will be reduced. in addition, there is a minimum inductor value required to maintain stability of the current loop ( given the fixed internal slope compensation). specifically, if the buck converter is going to be utilized at duty cycles over 40%, the inductance value must be at least l min , as given by the following equation: l min = 2.5 ? v out (h) table 1 depicts the recommended inductance for several common output voltages. table 1. buck recommended inductance output voltage minimum inductance maximum inductance 0.6v 1.5h 2.2h 1.2v 2.2h 4.7h 1.8v 3.3h 6.8h 2.5v 4.7h 8.2h buck output capacitor selection a low esr output capacitor should be utilized at the buck output in order to minimize voltage ripple. multilayer ce - ramic capacitors are an excellent choice as they have low esr and are available in small footprints. in addition to controlling the ripple magnitude, the value of the output capacitor also sets the loop crossover frequency and can, therefore, impact loop stability. there is both a minimum and maximum capacitance value required to ensure stabil - ity of the loop. if the output capacitance is too small, the loop crossover frequency will increase to the point where the switching delay and the high frequency parasitic poles of the error amplifier will degrade the phase margin. in addition, the wider bandwidth produced by a small output capacitor will make the loop more susceptible to switch - ing noise. at the other extreme, if the output capacitor is too large, the crossover frequency can decrease too far below the compensation zero and lead to a degraded phase margin. table 2 provides a guideline for the range of allowable values of low esr output capacitors. larger value output capacitors can be accommodated provided they have sufficient esr to stabilize the loop. table 2. buck output capacitor range v out c min c max 0.6v 15f 300f 0.8v 15f 230f 1.2v 10f 150f 1.8v 10f 90f 2.7v 10f 70f 3.3v 6.8f 50f ltc3521 3521fb for more information www.linear.com/ltc3521
15 buck input capacitor selection the pv in 2 pin provides current to the buck converter power switch and is the supply pin for the ics internal circuitry. it is recommended that a low esr ceramic capacitor with a value of at least 4.7 f be used to bypass this pin. the capacitor should be placed as close to the pin as possible and have a short return to ground. buck output voltage programming the output voltage is set by a resistive divider, according to the following formula: v out2,3 = 0.6v 1 + r2 r1 ? ? ? ? ? ? the external divider is connected to the output, as shown in figure 3. it is recommended that a feedforward capaci- tor, c ff , be placed in parallel with resistor r2 to improve the noise immunity of the feedback node. table 3 provides the recommended resistor and feedforward capacitor combinations for common output voltage options. table 3. buck resistor divider values v out r1 r2 c ff 0.6v C 0 C 0.8v 200k 69.8k 22pf 1.0v 118k 80.6k 22pf 1.2v 100k 102k 22pf 1.5v 78.7k 121k 22pf 1.8v 68.1k 137k 22pf 2.7v 63.4k 226k 33pf 3.3v 60.4k 274k 33pf buck-boost output voltage programming the buck-boost output voltage is set by a resistive divider according to the following formula: v out1 = 0.6v 1 + r2 r1 ? ? ? ? ? ? the external divider is connected to the output, as shown in figure 4. the buck-boost converter utilizes voltage mode control and the value of r2 plays an integral role in the dynamics of the feedback loop. in general, a larger value for r2 will increase stability and reduce the speed of the transient response. a smaller value of r2 will reduce stability but increase the transient response speed. a good starting point is to choose r 2 = 1 m, then calculate the required value of r1 to set the desired output voltage ac - cording to the above formula. if a large output capacitor is used, the bandwidth of the converter is reduced. in such cases r2 can be reduced to improve the transient response. if a large inductor or small output capacitor is utilized, the loop will be less stable and the phase margin can be improved by increasing the value of r2. buck-boost inductor selection to achieve high efficiency, a low esr inductor should be utilized for the buck-boost converter. the inductor must have a saturation rating greater than the worst case average inductor current plus half the ripple current. the peak-to-peak inductor current ripple will be larger in buck and boost mode than in the buck-boost region. the peak-to-peak inductor current ripple for each mode can applica t ions in f or m a t ion ltc3521 gnd 0.6v v out3 5.25v 0.6v v out2 5.25v fb3 r1 3521 f03 r2 fb2 r1 r2 figure 3. setting the buck output voltage ltc3521 gnd 1.8v v out1 5.25v fb1 r1 3521 f04 r2 figure 4. setting the buck-boost output voltage ltc3521 3521fb for more information www.linear.com/ltc3521
16 be calculated from the following formulas, where f is the frequency in mhz and l is the inductance in h: i l,p-p,buck = 1 fl ? v out v in C v out ( ) v in i l,p-p,boost = 1 fl ? v in v out C v in ( ) v out in addition to affecting output current ripple, the size of the inductor can also affect the stability of the feedback loop. in boost mode, the converter transfer function has a right half plane zero at a frequency that is inversely proportional to the value of the inductor. as a result, a large inductor can move this zero to a frequency that is low enough to degrade the phase margin of the feedback loop. it is recommended that the chosen inductor value be less than 10 h if the buck-boost converter is to be used in the boost region. buck-boost output capacitor selection a low esr output capacitor should be utilized at the buck- boost converter output in order to minimize output volt - age ripple . multilayer ceramic capacitors are an excellent choice as they have low esr and are available in small footprints. the capacitor should be chosen large enough to reduce the output voltage ripple to acceptable levels. neglecting the capacitor esr and esl, the peak-to-peak output voltage ripple can be calculated by the following formulas, where f is the frequency in mhz, c out is the capacitance in f, l is the inductance in h and i load is the output current in amps: v p-p,boost = i load v out C v in ( ) c out ? v out ? f v p-p,buck = 1 8 ? l ? c out ? f 2 ? v in C v out ( ) v out v in since the output current is discontinuous in boost mode, the ripple in this mode will generally be much larger than the magnitude of the ripple in buck mode. in addition to controlling the ripple magnitude, the value of the output capacitor also affects the location of the resonant frequency in the open loop converter transfer function. if the output capacitor is too small, the bandwidth of the converter will extend high enough to degrade the phase margin. to prevent this from happening, it is recommended that a minimum value of 10 f be used for the buck-boost output capacitor. buck-boost input capacitor selection the supply current to the buck- boost converter is provided by the pv in1 pin. it is recommended that a low esr ceramic capacitor with a value of at least 4.7 f be located as close to this pin as possible. inductor style and core material different inductor core materials and styles have an impact on the size and price of an inductor at any given peak current rating. toroid or shielded pot cores in ferrite or permalloy materials are small and reduce emissions, but generally cost more than powdered iron core induc - tors with similar electrical characteristics. the choice of inductor style depends upon the price, sizing, and emi requirements of a particular application. table 4 provides a sampling of inductors that are well suited to many ltc3521 application circuits. table 4. representative surface mount inductors manu- facturer part number v alue max current dcr height taiyo y uden np03sb4r7m 4.7h 1.2a 0.047 1.8mm np03sb6r8m 6.8h 1a 0.084 1.8mm coilcraft mss7341-502nl 5h 2.3a 0.024 4.1mm dt1608c-472ml 4.7h 1.2a 0.085 2.92mm cooper- bussmann sd7030-5r0-r 5h 2.4a 0.026 3mm sd20-6r2-r 6.2h 1.12a 0.072 2mm sumida cdr6d23mnnp-4r2 4.2h 2.6a 0.052 2.5mm cdrh4d16fb/nd- 6r8n 6.8h 1a 0.081 1.8mm applica t ions in f or m a t ion ltc3521 3521fb for more information www.linear.com/ltc3521
17 applica t ions in f or m a t ion capacitor vendor information both the input and output capacitors used with the ltc3521 must be low esr and designed to handle the large ac cur - rents generated by switching converters. the vendors in table 5 provide capacitors that are well suited to ltc3521 application circuits. table 5. capacitor vendor information manufacturer web site represent a tive part numbers taiyo yuden www.t-yuden.com jmk212bj106k 10f, 6.3v jmk212bj226k 22f, 6.3v tdk www.component. tdk.com c2012x5r0j106k 10f, 6.3v murata www.murata.com grm21br60j106k 10f, 6.3v grm32er61c226k 22f, 16v avx www.avxcorp.com sm055c106khn480 10f minimizing solution size is usually a priority. please be aware that ceramic capacitors can exhibit a significant reduction in effective capacitance when a bias is applied. the capacitors exhibiting the highest reduction are those packaged in the smallest case size. pcb layout considerations the ltc3521 switches large currents at high frequencies. special care should be given to the pcb layout to ensure stable, noise-free operation. figure 5 depicts the recom - mended pcb layout to be utilized for the ltc3521. a few key guidelines follow: 1. all cir culating high current paths should be kept as short as possible. this can be accomplished by keeping the routes to all bold components in figure 5 as short and as wide as possible. capacitor ground connections should via down to the ground plane in the shortest route possible. the bypass capacitors on pv in1 and pv in2 should be placed as close to the ic as possible and should have the shortest possible paths to ground. 2. the small - signal ground pad ( gnd) should have a single point connection to the power ground. a convenient way to achieve this is to short the pin directly to the exposed pad as shown in figure 5. 3. the components shown in bold, and their connections, should all be placed over a complete ground plane. 4. to prevent large circulating currents from disrupting the output voltage sensing, the ground for each resistor divider should be returned directly to the small signal ground pin (gnd). 5. use of vias in the die attach pad will enhance the ther - mal environment of the converter, especially if the vias extend to a ground plane region on the exposed bottom surface of the pcb. ltc3521 3521fb for more information www.linear.com/ltc3521
18 applica t ions in f or m a t ion figure 5. ltc3521 recommended pcb layout pgnd2 (18) sw3 (17) v out1 (16) sw1a (15) sw1b (14) nc (13) shdn2 (1) pgood3 (2) pgood2 (3) pgood1 (4) v in (5) gnd (6) buck v out buck v out via to ground plane 3521 f05 kelvin to v out pad kelvin to v out pad buck-boost v out kelvin to v out pad minimize trace length minimize trace length minimize trace length direct tie back to gnd pin uninterrupted ground plane must exist under all components shown in bold, and under traces connecting to those components fb2 (24) fb3 (23) pv in2 (22) pgnd1a (9) sw2 (20) nc (19) pwm (7) fb1 (8) shdn3 (9) shdn1 (10) pv in (11) pgnd1b (12) ltc3521 3521fb for more information www.linear.com/ltc3521
19 typical a pplica t ion dual supercapacitor to 3.3v at 200ma, 1.8v at 50ma and 1.2v at 100ma backup power supply converter output voltages efficiency vs v in + pv in1 pv in2 sw2 sw3 fb2 fb3 v out1 ltc3521 shdn2 shdn1 r1 1.0m r3 137k r4 68.1k c1 22f c2 10f c4 4.7f 1f + 1f l1 4.7h l2 4.7h v out1 3.3v 200ma v out2 1.8v 50ma r5 100k r6 100k c3 10f l3 4.7h v out3 1.2v 100ma v in 1.8v to 5.5v r2 221k 3521 ta02a shdn3 pwm sw1a sw1b fb1 pgood2 pgood1 pgood3 pgnd2gnd on off pwm burst pgnd1a pgnd1b v in v in (v) 1.8 efficiency (%) 76 84 92 2.8 3.8 4.8 100 72 80 88 96 3521 ta02c v out1 = 3.3v i out = 200ma v out2 = 1.8v i out = 50ma v out3 = 1.2v i out = 100ma 50s/div v in 2v/div v out2 2v/div v out3 2v/div v out1 2v/div 3521 ta02b ltc3521 3521fb for more information www.linear.com/ltc3521
20 p ackage descrip t ion fe package 20-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev j) exposed pad variation cb uf package 24-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1697 rev b) fe20 (cb) tssop rev j 1012 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref recommended solder pad layout 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 4 5 6 7 8 9 10 111214 13 6.40 ? 6.60* (.252 ? .260) 3.86 (.152) 2.74 (.108) 20 1918 17 16 15 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2 2.74 (.108) 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 3.86 (.152) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 20-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev j) exposed pad variation cb 4.00 0.10 (4 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wggd-x)?to be approved 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 2423 1 2 bottom view?exposed pad 2.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uf24) qfn 0105 rev b recommended solder pad pitch and dimensions 0.70 0.05 0.25 0.05 0.50 bsc 2.45 0.05 (4 sides) 3.10 0.05 4.50 0.05 package outline pin 1 notch r = 0.20 typ or 0.35 45 chamfer uf package 24-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1697 rev b) ltc3521 3521fb for more information www.linear.com/ltc3521
21 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 11/10 addition of pgnd1a reflected throughout data sheet addition of v in to typical applications 1, 19, 22 revised note 2 3 changes to block diagram 9 change to operation soft-start section 11, 13 b 08/13 corrected pin numbers on block diagram uf package 9 ltc3521 3521fb for more information www.linear.com/ltc3521
22 ? linear technology corporation 2010 lt 0813 rev b ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc3521 r ela t e d p ar t s part number description comments ltc3100 700ma i sw , 1.5mhz, synchronous step-up, 250ma synchronous step-down dc/dc converter and 100ma ldo 94% efficiency, v in : 0.7v to 5v, v out(max) = 5.25v, i q = 15a, i sd < 1a, 3mm 3mm qfn-16 package ltc3101 wide v in , multioutput dc/dc converter and powerpath? controller, 800ma buck-boost, dual 350ma buck converters, 50ma always-on ldo 95% efficiency, v in : 1.8v to 5.5v, i q = 38a, standby i q = 15a, 4mm 4mm qfn-24 package ltc3409 600ma i out , 1.7mhz/2.6mhz, synchronous step-down dc/ dc converter 96% efficiency, v in : 1.6v to 5.5v, v out(min) = 0.6v, i q = 65a, i sd < 1a, dfn package ltc3441/ltc3442/ ltc3443 1.2a i out , 2mhz, synchronous buck-boost dc/dc converter 95% efficiency, v in : 2.4v to 5.5v, v out(min) : 2.4v to 5.25v, i q = 50a, i sd < 1a, dfn package ltc3520 1a 2mhz, synchronous buck-boost and 600ma buck converter 95% efficiency, v in : 2.2v to 5.5v, v out(max) = 5.25v, i q = 55a, i sd < 1a, 4mm 4mm qfn-24 package ltc3522 400ma 2mhz, synchronous buck-boost and 200ma buck converter 95% efficiency, v in : 2.4v to 5.5v, v out(max) = 5.25v, i q = 25a, i sd < 1a, 3mm 3mm qfn-16 package ltc3531/ltc3531-3/ ltc 3531-3.3 200ma i out , 1.5mhz, synchronous buck-boost dc/dc converter 95% efficiency, v in : 1.8v to 5.5v, v out(min) : 2v to 5v, i q = 16a, i sd < 1a, thinsot and dfn packages ltc3532 500ma i out , 2mhz, synchronous buck-boost dc/dc converter 95% efficiency, v in : 2.4v to 5.5v, v out(min) : 2.4v to 5.25v, i q = 35a, i sd < 1a, ms10 and dfn packages ltc3547 dual 300ma i out , 2.25mhz, synchronous step-down dc/ dc converter 95% efficiency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 40a, i sd < 1a, dfn-8 package typical a pplica t ion li-ion to 3.3v at 800ma, 1.8v at 600ma and 1.2v at 600ma with sequenced start-up sequenced start-up waveforms pv in1 pv in2 sw2 v out1 fb2 fb1 sw3 ltc3521 shdn1 r5 100k r3 137k r4 68.1k c3 10f c2 10f 4.7f li-ion l1 4.7h l3 4.7h l2 4.7h v out2 1.8v 600ma r1 1.0m r2 221k c1 22f v out1 3.3v 800ma (1a, v in > 3.0v) v in 2.4v to 4.2v r6 100k 499k r5 499k 3521 ta03a pgood1 pgood3 pwm sw1a sw1b fb3 pgood2 shdn2 shdn3 pgood1 pgnd2 gnd pwm burst on off v out3 1.2v 600ma + pgnd1a pgnd1b v in 500s/div v out2 2v/div v out3 2v/div v out1 2v/div shdn2 , 5v/div pgood2, 5v/div pgood3, 5v/div 3521 ta03b ltc3521 3521fb for more information www.linear.com/ltc3521

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